diff options
| -rw-r--r-- | nes/bus.go | 21 | ||||
| -rw-r--r-- | nes/nes.go | 34 | ||||
| -rw-r--r-- | tests/nestest_test.go | 29 |
3 files changed, 57 insertions, 27 deletions
diff --git a/nes/bus.go b/nes/bus.go new file mode 100644 index 0000000..480d178 --- /dev/null +++ b/nes/bus.go @@ -0,0 +1,21 @@ +package nes + +func (n *Console) Read(addr uint16) uint8 { + switch { + case addr < 0x2000: + return n.RAM[addr&0x7FF] + case addr >= 0x4020: + return n.Cart.Mapper.CPURead(addr) + default: + return 0 + } +} + +func (n *Console) Write(addr uint16, v uint8) { + switch { + case addr < 0x2000: + n.RAM[addr&0x7FF] = v + case addr >= 0x4020: + n.Cart.Mapper.CPUWrite(addr, v) + } +}
\ No newline at end of file diff --git a/nes/nes.go b/nes/nes.go new file mode 100644 index 0000000..c4d09a0 --- /dev/null +++ b/nes/nes.go @@ -0,0 +1,34 @@ +package nes + +import ( + "crecher.net/gones/v2/cart" + "crecher.net/gones/v2/cpu" +) + +type Console struct { + CPU *cpu.CPU + Cart *cart.Cartridge + RAM [0x800]uint8 + // PPU, APU, controllers once they exist + cycles uint64 +} + +func New(c *cart.Cartridge) *Console { + n := &Console{Cart: c} + n.CPU = cpu.NewCPU(n) + n.CPU.Reset() + return n +} + +func (n *Console) Step() int { + cycles := n.CPU.Step() + n.cycles += uint64(cycles) + return cycles +} + +func (n *Console) StepFrame() { + const cyclesPerFrame = 29780 // 29780 ~ 1789773 / 60.1 + for done := 0; done < cyclesPerFrame; { + done += n.Step() + } +}
\ No newline at end of file diff --git a/tests/nestest_test.go b/tests/nestest_test.go index de98156..41bc6f8 100644 --- a/tests/nestest_test.go +++ b/tests/nestest_test.go @@ -8,34 +8,9 @@ import ( "testing" "crecher.net/gones/v2/cart" - "crecher.net/gones/v2/cpu" + "crecher.net/gones/v2/nes" ) -type nestestBus struct { - ram [0x0800]uint8 - cart cart.Mapper -} - -func (b *nestestBus) Read(addr uint16) uint8 { - switch { - case addr < 0x2000: - return b.ram[addr%0x0800] - case addr >= 0x4020: - return b.cart.CPURead(addr) - default: - return 0 - } -} - -func (b *nestestBus) Write(addr uint16, v uint8) { - switch { - case addr < 0x2000: - b.ram[addr%0x0800] = v - case addr >= 0x4020: - b.cart.CPUWrite(addr, v) - } -} - type cpuState struct { pc uint16 a, x, y, p, sp uint8 @@ -95,7 +70,7 @@ func TestNestest(t *testing.T) { t.Fatal("no log lines parsed") } - core := cpu.NewCPU(&nestestBus{cart: c.Mapper}) + core := nes.New(c).CPU core.PC = 0xC000 core.SP = 0xFD core.Status = 0x24 |