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authorcrecher <crecher@crecher.net>2026-10-12 04:27:53 +0200
committercrecher <crecher@crecher.net>2026-10-12 04:27:53 +0200
commitfe7ae6e696811a39828dd9727295aa73ae4e5873 (patch)
tree503f3c353cbd9e10714df80999da1738d13eb180 /tests
parentbe4d8cb438b1b0f0a66681adc319875b5ee69eed (diff)
downloadgones-fe7ae6e696811a39828dd9727295aa73ae4e5873.tar.gz
gones-fe7ae6e696811a39828dd9727295aa73ae4e5873.zip
nes: add console with cpu bus and step loop
tests: run nestest through nes console
Diffstat (limited to 'tests')
-rw-r--r--tests/nestest_test.go29
1 files changed, 2 insertions, 27 deletions
diff --git a/tests/nestest_test.go b/tests/nestest_test.go
index de98156..41bc6f8 100644
--- a/tests/nestest_test.go
+++ b/tests/nestest_test.go
@@ -8,34 +8,9 @@ import (
"testing"
"crecher.net/gones/v2/cart"
- "crecher.net/gones/v2/cpu"
+ "crecher.net/gones/v2/nes"
)
-type nestestBus struct {
- ram [0x0800]uint8
- cart cart.Mapper
-}
-
-func (b *nestestBus) Read(addr uint16) uint8 {
- switch {
- case addr < 0x2000:
- return b.ram[addr%0x0800]
- case addr >= 0x4020:
- return b.cart.CPURead(addr)
- default:
- return 0
- }
-}
-
-func (b *nestestBus) Write(addr uint16, v uint8) {
- switch {
- case addr < 0x2000:
- b.ram[addr%0x0800] = v
- case addr >= 0x4020:
- b.cart.CPUWrite(addr, v)
- }
-}
-
type cpuState struct {
pc uint16
a, x, y, p, sp uint8
@@ -95,7 +70,7 @@ func TestNestest(t *testing.T) {
t.Fatal("no log lines parsed")
}
- core := cpu.NewCPU(&nestestBus{cart: c.Mapper})
+ core := nes.New(c).CPU
core.PC = 0xC000
core.SP = 0xFD
core.Status = 0x24