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Diffstat (limited to 'cpu')
-rw-r--r--cpu/cpu.go12
-rw-r--r--cpu/instructions.go5
-rw-r--r--cpu/opcodes.go13
3 files changed, 30 insertions, 0 deletions
diff --git a/cpu/cpu.go b/cpu/cpu.go
index 79199a2..fb673b7 100644
--- a/cpu/cpu.go
+++ b/cpu/cpu.go
@@ -16,6 +16,7 @@ type CPU struct {
Bus Bus
Cycles uint64
+ Jammed bool
extraCycles int
}
@@ -65,9 +66,13 @@ func (c *CPU) Reset() {
c.Status = FlagU | FlagI
c.PC = c.read16(vectorReset)
c.Cycles = 7
+ c.Jammed = false
}
func (c *CPU) IRQ() {
+ if c.Jammed {
+ return
+ }
if c.flag(FlagI) {
return
}
@@ -76,6 +81,9 @@ func (c *CPU) IRQ() {
}
func (c *CPU) NMI() {
+ if c.Jammed {
+ return
+ }
c.interrupt(vectorNMI, false)
c.Cycles += 7
}
@@ -94,6 +102,10 @@ func (c *CPU) interrupt(vector uint16, brk bool) {
}
func (c *CPU) Step() int {
+ if c.Jammed {
+ c.Cycles++
+ return 1
+ }
before := c.Cycles
opcode := c.read(c.PC)
diff --git a/cpu/instructions.go b/cpu/instructions.go
index b390f5c..b74a2db 100644
--- a/cpu/instructions.go
+++ b/cpu/instructions.go
@@ -221,3 +221,8 @@ func iscExec(c *CPU, op operand) {
c.writeOperand(op, v)
c.addWithCarry(^v)
}
+
+func jamExec(c *CPU, op operand) {
+ c.Jammed = true
+ c.PC--
+}
diff --git a/cpu/opcodes.go b/cpu/opcodes.go
index 00b1563..13f9612 100644
--- a/cpu/opcodes.go
+++ b/cpu/opcodes.go
@@ -235,6 +235,19 @@ func init() {
def(0xDC, "NOP", ModeAbsoluteX, 4, true, nopExec)
def(0xFC, "NOP", ModeAbsoluteX, 4, true, nopExec)
+ def(0x02, "JAM", ModeImplied, 2, false, jamExec)
+ def(0x12, "JAM", ModeImplied, 2, false, jamExec)
+ def(0x22, "JAM", ModeImplied, 2, false, jamExec)
+ def(0x32, "JAM", ModeImplied, 2, false, jamExec)
+ def(0x42, "JAM", ModeImplied, 2, false, jamExec)
+ def(0x52, "JAM", ModeImplied, 2, false, jamExec)
+ def(0x62, "JAM", ModeImplied, 2, false, jamExec)
+ def(0x72, "JAM", ModeImplied, 2, false, jamExec)
+ def(0x92, "JAM", ModeImplied, 2, false, jamExec)
+ def(0xB2, "JAM", ModeImplied, 2, false, jamExec)
+ def(0xD2, "JAM", ModeImplied, 2, false, jamExec)
+ def(0xF2, "JAM", ModeImplied, 2, false, jamExec)
+
def(0xEB, "SBC", ModeImmediate, 2, false, sbcExec)
def(0xA7, "LAX", ModeZeroPage, 3, false, laxExec)